Sarmad Dahir
Sr. Principal Application Engineer
Cadence Design Systems
Date and time: April 20, 2024, 1:00 p.m. Central Time
Title: Stratus High-Level Synthesis enables full-flow hardware design automation and optimization
Summary: In this presentation we will explain the advantages of constructing digital hardware using Higher-Level Languages such as C++/SystemC, or MathWorks MATLAB-code. These higher-level models are synthesized directly to Hardware using the full Cadence Digital Implementation Solution. We will delve into the design space exploration and optimization and explain how the Cadence Stratus HLS technology along with Logic-Synthesis (Genus), RTL Power Analysis (Joules), Equivalence Checking (Jasper), and Machine Learning (Cerebrus) can produce optimal production quality hardware and dramatically decrease the design implementation cycle. As a result, the overall design Power, Performance, and Area are optimized while significantly shortening the project Schedule at the same time.
Sarmad Dahir graduated from the Royal Institute of Technology (KTH), Stockholm, Sweden, in 2007 with a M.Sc. EE specializing in IC microelectronics design.
He currently serves as a Sr. Principal Engineer at Cadence Design Systems, Sarmad is supporting hardware front-end design and implementation tools, particularly specializing in Stratus High-Level Synthesis technology.
Sarmad’s career includes experience from working as an ASIC/FPGA designer and verification engineer for IC industry leading companies such as Ericsson and Samsung.